POLYSILICON N+P-N+ STRUCTURES FOR MEMORY REDUNDANCY

被引：9

作者：

GREVE, DW

TRAN, LV

机构：

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 1982年 / 29卷 / 08期

关键词：

D O I：

10.1109/T-ED.1982.20873

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：1313 / 1318

页数：6

共 17 条

[1]

ANTHONY TR, 1981, J APPL PHYS, V51, P6356

[2]

BINDELS JFM, 1981, ISSCC DIGEST TECHNIC, P82

[3] HIGH-SPEED DROPLET MIGRATION IN SILICON [J].

CLINE, HE ;

ANTHONY, TR .

JOURNAL OF APPLIED PHYSICS, 1976, 47 (06) :2325-2331

[4]

CROOK DL, 1981, 19TH ANN P REL PHYS, P1

[5] GRAIN-BOUNDARY STATES AND THE CHARACTERISTICS OF LATERAL POLYSILICON DIODES [J].

DEGRAAFF, HC ;

HUYBERS, M ;

DEGROOT, JG .

SOLID-STATE ELECTRONICS, 1982, 25 (01) :67-71

[6]

EATON SS, 1981, ISSCC DIG TECH PAPER, P84

[7] PROGRAMMING MECHANISM OF POLYSILICON RESISTOR FUSES [J].

GREVE, DW .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1982, 29 (04) :719-724

[8]

Kodera H., 1963, JAP J APPL PHYS, V2, P212, DOI [10.1143/JJAP.2.212, DOI 10.1143/JJAP.2.212]

[9]

KOKKONEN K, 1981, ISSCC DIG TECH PAPER, P80

[10] A FAULT-TOLERANT 256K RAM FABRICATED WITH MOLYBDENUM-POLYSILICON TECHNOLOGY [J].

MANO, T ;

TAKEYA, K ;

WATANABE, T ;

IEDA, N ;

KIUCHI, K ;

ARAI, E ;

OGAWA, T ;

HIRATA, K .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1980, 15 (05) :865-872

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