LIMITS OF NANO-GATE FABRICATION

被引：12

作者：

ALLEE, DR ^{[1
]}

BROERS, AN ^{[1
]}

PEASE, RFW ^{[1
]}

机构：

[1] STANFORD UNIV,DEPT ELECT ENGN,STANFORD,CA 94305

来源：

PROCEEDINGS OF THE IEEE | 1991年 / 79卷 / 08期

关键词：

D O I：

10.1109/5.92069

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper reviews the limits of nanometer scale gate electrode (nano-gate) fabrication. The technology to fabricate nano-gates has become increasingly important in recent years as the scaling limits of conventional electronic devices and the quantum effects of novel devices are investigated. Consistant with the technology used to fabricate virtually all of the smallest devices to date, the emphasis is on the resolution limits of electron beam lithography and associated ultrahigh resolution resists. Recent results of directly patterning SiO2 with nanometer scale resolution by e-beam exposure through a sacrificial layer are also presented. Finally, because the high resistance normally associated with nanometer scale electrodes seriously limits the performance of high frequency devices, various techniques to reduce the gate resistance are compared.

引用

页码：1093 / 1105

页数：13

共 68 条

[1] DIRECT NANOMETER SCALE PATTERNING OF SIO2 WITH ELECTRON-BEAM IRRADIATION THROUGH A SACRIFICIAL LAYER [J].