A 10-GHZ 8-B MULTIPLEXER DEMULTIPLEXER CHIP SET FOR THE SONET STS-192 SYSTEM

被引：14

作者：

ISHIDA, K ^{[1
]}

WAKIMOTO, H ^{[1
]}

YOSHIHARA, K ^{[1
]}

KONNO, M ^{[1
]}

SHIMIZU, S ^{[1
]}

KITAURA, Y ^{[1
]}

TOMITA, K ^{[1
]}

SUZUKI, T ^{[1
]}

UCHITOMI, N ^{[1
]}

机构：

[1] TOSHIBA CO LTD,CTR RES & DEV,KAWASAKI 210,JAPAN

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1991年 / 26卷 / 12期

关键词：

D O I：

10.1109/4.104187

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An ultrahigh-speed 8-b multiplexer (MUX) and demultiplexer (DMUX) chip set has been developed for the synchronous optical network (SONET) next-generation optical-fiber communication systems, which will require data bit rates of about 10 Gb/s. These IC's were designed using three novel concepts: a tree-type architecture giving reliable operation, a dynamic divider with a wide operating range, and a 50-OMEGA on-chip transmission line with high-speed pulse propagation. They were fabricated using a 0.5-mu-m WNx-gate GaAs MESFET process. The DMUX and MUX operated up to 10.4 and 11.4 GHz, respectively, both with an adequate phase margin of more than 230-degrees.

引用

页码：1936 / 1943

页数：8

共 13 条

[1] 11.4 GBIT/S MULTIPLEXER IC EMPLOYING SUB-MICRON SI BIPOLAR TECHNOLOGY FOR USE IN FUTURE BROAD-BAND TELECOMMUNICATIONS SYSTEMS [J].