A NEW CIRCUIT MODEL FOR TUNNELING RELATED TRAPPING AT INSULATOR-SEMICONDUCTOR INTERFACES IN ACCUMULATION

被引：22

作者：

MUI, DSL ^{[1
]}

REED, J ^{[1
]}

BISWAS, D ^{[1
]}

MORKOC, H ^{[1
]}

机构：

[1] UNIV ILLINOIS,MAT RES LAB,URBANA,IL 61801

来源：

JOURNAL OF APPLIED PHYSICS | 1992年 / 72卷 / 02期

关键词：

D O I：

10.1063/1.351887

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

We have investigated the effects due to the capture of tunneling electrons by interface traps to the measured capacitance, C(m), and equivalent series resistance, R(m), of insulator-semiconductor interfaces in metal-insulator-semiconductor (MIS) capacitors in accumulation. A new circuit model taking into account the capture of tunneling electrons by interface traps is derived. Theoretical and experimental results of Si3N4/Si/GaAs, Si3N4/epi-Si, and SiO2/epi-Si MIS capacitors are compared. The Si, Si3N4, and SiO2 layers investigated were deposited in situ by electron cyclotron resonance generated plasma in an ultrahigh vacuum chemical vapor deposition chamber. Frequency dispersion of both C(m) and R(m) can be adequately explained by the new circuit model.

引用

页码：553 / 558

页数：6

共 16 条

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