LSI YIELD MODELING AND PROCESS MONITORING

[1] COMPUTATION OF INTEGRATED-CIRCUIT YIELDS FROM DISTRIBUTION OF SLICE YIELDS FOR INDIVIDUAL DEVICES [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1968, ED15 (06) : 405 - &

[2] DENNARD RA, COMMUNICATION

[3] DEFECT ANALYSIS AND YIELD DEGRADATION OF INTEGRATED-CIRCUITS [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1974, SC 9 (03) : 96 - 103

[4] 8K B RANDOM-ACCESS MEMORY CHIP USING ONE-DEVICE FET CELL [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1973, SC 8 (05) : 298 - 305

[5] LAWSON TR, 1966, SOLID STATE TECHNOL, V7, P22

[6] MOORE GE, 1970, ELECTRONICS, V43, P126

[7] COST-SIZE OPTIMA OF MONOLITHIC INTEGRATED CIRCUITS [J]. PROCEEDINGS OF THE IEEE, 1964, 52 (12) : 1537 - &

[8] SEEDS RB, 1967, 1967 IEEE INT CONV 6, P60

[9] DEFECT DENSITY DISTRIBUTION FOR LSI YIELD CALCULATIONS [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1973, ED20 (07) : 655 - 657

[10] THOMAS DR, 1974, GOV MICROCIRCUIT APP, P196

[1] COMPUTATION OF INTEGRATED-CIRCUIT YIELDS FROM DISTRIBUTION OF SLICE YIELDS FOR INDIVIDUAL DEVICES [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1968, ED15 (06) : 405 - &

[2] DENNARD RA, COMMUNICATION

[3] DEFECT ANALYSIS AND YIELD DEGRADATION OF INTEGRATED-CIRCUITS [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1974, SC 9 (03) : 96 - 103

[4] 8K B RANDOM-ACCESS MEMORY CHIP USING ONE-DEVICE FET CELL [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1973, SC 8 (05) : 298 - 305

[5] LAWSON TR, 1966, SOLID STATE TECHNOL, V7, P22

[6] MOORE GE, 1970, ELECTRONICS, V43, P126

[7] COST-SIZE OPTIMA OF MONOLITHIC INTEGRATED CIRCUITS [J]. PROCEEDINGS OF THE IEEE, 1964, 52 (12) : 1537 - &

[8] SEEDS RB, 1967, 1967 IEEE INT CONV 6, P60

[9] DEFECT DENSITY DISTRIBUTION FOR LSI YIELD CALCULATIONS [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1973, ED20 (07) : 655 - 657

[10] THOMAS DR, 1974, GOV MICROCIRCUIT APP, P196