AN ANALYTICAL MAXIMUM TOGGLE FREQUENCY EXPRESSION AND ITS APPLICATION TO OPTIMIZING HIGH-SPEED ECL FREQUENCY-DIVIDERS

A novel method has been used to analyze static and regenerative frequency dividers by relating their performance to that of the constituent exclusive-or (xor) gates. It has been found that the behavior of the propagation delay of xor gates is quite linear and this has allowed the derivation of a propagation delay expression for xor gates using a sensitivity analysis. The validity of the expression has been carefully checked by comparison with SPICE simulations and with reported results in the literature, and agreement to 10% has been obtained. In order to optimize frequency dividers, figures of merit for frequency dividers realized in silicon and AlGaAs/GaAs technologies are proposed. Expressions for optimum load resistance Qpj, and hence optimum collector current density /(-> then derived from these figure-of-merit expressions. By comparing the optimum collector current densities with the current densities at which the maximum ff occurs, it is found that improved performance can be obtained for silicon technology by designing transistors in which tbe maximum fj occurs at a higher collector current density. For AlGaAs/GaAs technology, improved performance requires general reductions in Rg, and Rg^. This conclusion is consistent with results obtained on ECL and CML ring oscillators Q], thereby demonstrating that the use of a ring oscillator to optimize the fabrication process and transistor design should automatically lead to an optimum value for the maximum toggle frequency of a frequency divider. © 1990 IEEE