EVALUATION OF Q(BD) FOR ELECTRONS TUNNELING FROM THE SI/SIO2 INTERFACE COMPARED TO ELECTRON-TUNNELING FROM THE POLY-SI/SIO2 INTERFACE

Electrical time to breakdown (TTB) measurements show the charge to breakdown (Q(bd)) of gate oxide capacitors fabricated on n-type well (n-well) substrates always to be higher than that of capacitors on p-type well (p-well) substrates on the same wafer when both are biased into accumulation under normal test conditions. In this paper, we correlate the higher n-well Q(bd) to i) smooth capacitor oxide/substrate interfaces, and ii) minimized grain boundary cusps at the poly-Si gate/oxide interfaces. We confirm that Fowler-Nordheim tunneling is the dominant current conduction mechanism through the oxide. We correlate higher Q(bd) to higher barrier height for a given substrate type. We observe also that the slope of the barrier height versus temperature plot is lower for both p-well and n-well cases with electrons tunneling from the silicon substrate. We speculate that this is the result of surface roughness at the poly-Si gate/SiO2 interface. This causes higher electric field and lower barrier height and Q(bd) degrades more with temperature increases than for electrons tunneling from the Si/SiO2 interface. An improved poly-Si gate deposition and annealing process with clean, smooth oxide/substrate interfaces will improve the p-well breakdown characteristics and higher Q(bd) can be achieved for the p-well capacitors under normal test conditions.