256-KBIT BUBBLE MEMORY CHIP FABRICATION AND CHARACTERIZATION

被引：9

作者：

TSUZUKI, N

YAMAMOTO, M

HYUGA, F

机构：

[1] Musashino Electrical Communication Laboratory, Nippon Telegraph and Telephone Public Corporation, Musashino-shi, Tokyo

来源：

JOURNAL OF APPLIED PHYSICS | 1979年 / 50卷 / 03期

关键词：

D O I：

10.1063/1.327060

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

A 256 kbit bubble memory chip, which uses asymmetric chevron propagation elements has been designed, fabricated and characterized. Average circuit period is 8 μm and minimum feature size is 1 μm for all chip functions. Chip size is 4.5 mm×5.1 mm. A new stretcher detector and a planar chip structure enable the 256 kbit chip to operate at low rotating field. For a typical device processed on a (YSmLu)3(FeGa)5O 12 magnetic garnet film, the overall bias margin for all functions is 15 Oe with a 50 Oe circular rotating field at 200 kHz.

引用

页码：2219 / 2221

页数：3

共 11 条

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[10]

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