Testing asynchronous circuits: A survey

被引:43
作者
Hulgaard, H
Burns, SM
Borriello, G
机构
[1] Department of Computer Science and Engineering, University of Washington, Seattle
关键词
asynchronous circuits; stuck-at fault testing; path delay fault testing; self-checking circuits; test generation;
D O I
10.1016/0167-9260(95)00012-5
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Asynchronous circuit design has been studied for decades, but it has only recently been feasible to construct large and efficient asynchronous systems. The inherent differences between asynchronous and synchronous circuits, primarily that asynchronous circuits do not have a global clock, necessitate a review of the testing techniques used for synchronous circuits and a re-evaluation of the trade-offs involved. This paper surveys different techniques for checking whether an asynchronous circuit has fabrication defects. These techniques include approaches to self-checking design, methods for test generation, design for testability, and delay test of asynchronous circuits.
引用
收藏
页码:111 / 131
页数:21
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