A TUTORIAL ON BUILT-IN SELF-TEST .2. APPLICATIONS

被引：83

作者：

AGRAWAL, VD ^{[1
]}

KIME, CR ^{[1
]}

SALUJA, KK ^{[1
]}

机构：

[1] UNIV WISCONSIN,MADISON,WI 53706

来源：

IEEE DESIGN & TEST OF COMPUTERS | 1993年 / 10卷 / 02期

基金：

美国国家科学基金会;

关键词：

D O I：

10.1109/54.211530

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Concluding an overview of built-in self-test (BIST) concepts and practices, Part 2 covers BIST hardware structures, applications, and tools. The authors describe testing approaches for general and structured logic. They illustrate BIST techniques with real-world examples and present hardware structures and software tools supporting BIST design.

引用

页码：69 / 77

页数：9

共 33 条

[1]

ABADIR MA, 1989, P INT C COMPUTER AID, P562

[2] A KNOWLEDGE-BASED SYSTEM FOR DESIGNING TESTABLE VLSI CHIPS [J].

ABADIR, MS ;

BREUER, MA .

IEEE DESIGN & TEST OF COMPUTERS, 1985, 2 (04) :56-68

[3]

ABRAMOVICI M, 1991, DIGITAL SYSTEMS TEST

[4]

Bardell P. H., 1990, Journal of Electronic Testing: Theory and Applications, V1, P73, DOI 10.1007/BF00134016

[5]

BARDELL PH, 1987, BUILT TEST VLSI PSEU

[6]

Bleeker H., 1993, BOUNDARY SCAN TEST P

[7] A TESTABILITY STRATEGY FOR MULTIPROCESSOR ARCHITECTURE [J].

CATTHOOR, F ;

VANSAS, J ;

INZE, L ;

DEMAN, H .

IEEE DESIGN & TEST OF COMPUTERS, 1989, 6 (02) :18-34

[8] REALISTIC BUILT-IN SELF-TEST FOR STATIC RAMS [J].

DEKKER, R ;

BEENKER, F ;

THIJSSEN, L .

IEEE DESIGN & TEST OF COMPUTERS, 1989, 6 (01) :26-34

[9] BUILT-IN SELF-TESTING OF RANDOM-ACCESS MEMORIES [J].

FRANKLIN, M ;

SALUJA, KK .

COMPUTER, 1990, 23 (10) :45-56

[10] AN AUTOMATIC DFT SYSTEM FOR THE SILC SILICON COMPILER [J].

FUNG, HS ;

HIRSCHHORN, S .

IEEE DESIGN & TEST OF COMPUTERS, 1986, 3 (01) :45-57

← 1 2 3 4 →