VELOCITY SATURATION IN THE EXTRINSIC DEVICE - A FUNDAMENTAL LIMIT IN HFETS

We have carried out an experimental study revealing that velocity saturation (v(sat)) occurring in both the extrinsic source and drain sets a fundamental limit on maximum drain current and useful gate swing in HFET's. Using AlGaAs/ n+-InGaAs HFET's as a vehicle, we find that first g(m) and eventually f(T) decline at high currents in two stages. Initially, the approach of v(sat) in the extrinsic device causes the small-signal source and drain resistances (r(s) and r(d)) to rise dramatically, primarily degrading g(m). As the current increases further, the large-signal source and drain resistances (R(s) and R(d)) grow Significantly as well, pushing the intrinsic HFET toward the linear regime. Combined with the rapid rise of r(s) and r(d), the accompanying increase in gate-drain capacitance forces f(T) to decline through a strongly enhanced Miller effect. We associate this two-fold mechanism with a new regime of HFET operation, which we call the parasitic-resistance blow-up regime.