A UNIFIED ANALYTICAL MODEL FOR DRAIN-INDUCED BARRIER LOWERING AND DRAIN-INDUCED HIGH ELECTRIC-FIELD IN A SHORT-CHANNEL MOSFET

被引：9

作者：

JAIN, SC

BALK, P

机构：

[1] INDIAN INST TECHNOL,NEW DELHI 110016,INDIA

[2] RHEIN WESTFAL TH AACHEN,INST SEMICOND ELECTR,D-5100 AACHEN,FED REP GER

来源：

关键词：

D O I：

10.1016/0038-1101(87)90205-X

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

SEMICONDUCTOR DEVICES, MOSFET

引用

页码：503 / 511

页数：9

共 25 条

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TERRILL, KW ;

HU, C ;

KO, PK .

[24] VLSI LIMITATIONS FROM DRAIN-INDUCED BARRIER LOWERING [J].

TROUTMAN, RR .

[25] THRESHOLD VOLTAGE IN SHORT-CHANNEL MOS DEVICES [J].

VISWANATHAN, CR ;

BURKEY, BC ;

LUBBERTS, G ;

TREDWELL, TJ .