A 5-V ONLY 16-KBIT STACKED-CAPACITOR MOS RAM

被引：10

作者：

KOYANAGI, M ^{[1
]}

SAKAI, Y ^{[1
]}

ISHIHARA, M ^{[1
]}

TAZUNOKI, M ^{[1
]}

HASHIMOTO, N ^{[1
]}

机构：

[1] HITACHI LTD,CTR DEVICE DEV,TOKYO 187,JAPAN

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 1980年 / 27卷 / 08期

关键词：

D O I：

10.1109/T-ED.1980.20076

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：1596 / 1601

页数：6

共 11 条

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[3]

ITO K, 1978, ESSCIRC TECH DIG, P103

[4]

Koyanagi M., 1979, JPN J APPL PHYS S, V18

[5]

KOYANAGI M, 1978, IEDM, P348

[6]

Lee H. S., 1976, International Electron Devices Meeting. (Technical digest), P15

[7]

MOHSEN A, 1979, ISSCC DIG TECH PAPER, P152

[8]

PASHLEY P, 1977, ELECTRONICS 0818, P252

[9] CHARGE-COUPLED RAM CELL CONCEPT [J].

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FU, HS .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1976, 23 (02) :126-131

[10] HI-C RAM CELL CONCEPT [J].

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