QUALIFYING COMMERCIAL ICS FOR SPACE TOTAL-DOSE ENVIRONMENTS

A test protocol based on MIL-STD-883D, Test Method 1019.4, which includes a room-temperature biased anneal following irradiation, is shown to predict device response to low dose-rate irradiations more accurately than the present standard. In this work we measure failure dose with three different test protocols: 1) with method 1019.4, 2) with Method 1019.4 plus a room-temperature anneal, and 3) with 0.2 rad(Si)/s irradiations at static and dynamic bias. In comparing the power-supply current (I(DD)) of two commercial field-programmable gate arrays (FPGAs), we found that the failure dose for devices with a high annealing rate increased by a factor of 10 times when a room-temperature anneal is included, while devices with a slower annealing rate showed almost a 2-times improvement in failure dose. Slower-annealing devices showed a higher failure dose when dynamically biased during low dose-rate irradiations, indicating that radiation-induced charge neutralization accelerated recovery in these devices. Recommendations are provided on methods to characterize the hardness of MOS ICs using a test flow that includes room-temperature in addition to elevated temperature anneals.