SCHOTTKY-BASE I2L - HIGH-PERFORMANCE LSI TECHNOLOGY

A new I2L technology is described which offers significant advantages in packing density, device performance, and reduced LSI circuit complexity as compared to the conventional I2L. The basic logic gate in this design is a multiinput, multioutput NAND gate which consists of a p-n-p switch and an n-p-n injector. Schottky diodes are formed on the p-n-p base which is merged with the n-p-n (injector) collector. This I2L technology also offers convenient interfacing with other standard IC parts. (Totem pole and 3-state logic levels can be made available on chip.) Experimental data on a test chip indicate a p-n-p current gain of ∼50, TTL-type n-p-n current gain of ∼80, a delay-power product of 0.5 pJ, and a minimum delay of 10 ns for devices using 7.5 µm minimum linewidths. Based on theoretical calculations, a minimum delay time of 1.5 ns at a power dissipation of 50 to 75 µW/gate is projected for oxide-isolated scaled-down Schottky-base I2L gates with 1 to 1.5 µm minimum linewidths. Copyright © 1979 by The Institute Of Electrical And Electronics Engineers, Inc.