EFFECT OF ANNEALING ON POLYSILICON EMITTER TRANSISTORS

被引:5
作者
KEYES, EP
TARR, NG
机构
关键词
D O I
10.1139/p89-031
中图分类号
O4 [物理学];
学科分类号
0702 ;
摘要
引用
收藏
页码:179 / 183
页数:5
相关论文
共 15 条
[1]   COMPARISON OF EXPERIMENTAL AND THEORETICAL RESULTS ON POLYSILICON EMITTER BIPOLAR-TRANSISTORS [J].
ASHBURN, P ;
SOEROWIRDJO, B .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1984, 31 (07) :853-860
[2]  
CHOR EF, 1983, IEEE ELECTRON DEVICE, V6, P516
[3]   SIS TUNNEL EMITTER - THEORY FOR EMITTERS WITH THIN INTERFACE LAYERS [J].
DEGRAAFF, HC ;
DEGROOT, JG .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1979, 26 (11) :1771-1776
[4]  
GETREU IE, 1978, MODELING BIPOLAR TRA, P140
[5]   SUPERBETA POLYSILICON EMITTER TRANSISTORS [J].
KEYES, EP ;
TARR, NG .
IEEE ELECTRON DEVICE LETTERS, 1987, 8 (07) :312-314
[6]  
LOH WH, 1985, IEEE ELECTRON DEV LE, V6, P44
[8]   EXPERIMENTAL-STUDY OF THE MINORITY-CARRIER TRANSPORT AT THE POLYSILICON MONOSILICON INTERFACE [J].
NEUGROSCHEL, A ;
ARIENZO, M ;
KOMEM, Y ;
ISAAC, RD .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1985, 32 (04) :807-816
[9]  
NG CC, 1986, TECH DIGEST IEDM86, P32
[10]   METHOD FOR DETERMINING THE EMITTER AND BASE SERIES RESISTANCES OF BIPOLAR-TRANSISTORS [J].
NING, TH ;
TANG, DD .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1984, 31 (04) :409-412