A 20-NS 128-KBIT X 4 HIGH-SPEED DRAM WITH 330-MBIT/S DATA RATE

被引：13

作者：

LU, NCC ^{[1
]}

CHAO, HH ^{[1
]}

HWANG, W ^{[1
]}

HENKELS, WH ^{[1
]}

RAJEEVAKUMAR, TV ^{[1
]}

HANAFI, HI ^{[1
]}

TERMAN, LM ^{[1
]}

FRANCH, RL ^{[1
]}

机构：

[1] IBM CORP,THOMAS J WATSON RES CTR,DIV GEN TECHNOL,YORKTOWN HTS,NY 10598

来源：

关键词：

D O I：

10.1109/4.5936

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：1140 / 1149

页数：10

共 13 条

[1] CHAO H, 1987, Patent No. 4678941
[2] A 70 NS HIGH-DENSITY 64K CMOS DYNAMIC RAM
CHWANG, RJC
CHOI, M
CREEK, D
STERN, S
PELLEY, PH
SCHUTZ, JD
WARKENTIN, PA
BOHR, MT
YU, K
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1983, 18 (05) : 457 - 463
[3] HORI R, 1987, ISSCC, P280
[4] HALF-VDD BIT-LINE SENSING SCHEME IN CMOS DRAMS
LU, NCC
CHAO, HH
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1984, 19 (04) : 451 - 454
[5] PLATE-NOISE ANALYSIS OF AN ON-CHIP GENERATED HALF-VDD BIASED-PLATE PMOS CELL IN CMOS DRAMS
LU, NCC
CHAO, HH
HWANG, W
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1985, 20 (06) : 1272 - 1276
[6] LU NCC, 1988, ISSCC, P240
[7] LU NCC, 1988, ISSCC, P98
[8] MADLINE P, 1983, IEEE ICCD P, P379
[9] RAJEEVAKUMAR T, IN PRESS NEW FAILURE
[10] A 30-MU-A DATA-RETENTION PSEUDOSTATIC RAM WITH VIRTUALLY STATIC RAM MODE
SAWADA, K
SAKURAI, T
NOGAMI, K
SATO, K
SHIROTORI, T
KAKUMU, M
MORITA, S
KINUGAWA, M
ASAMI, T
NARITA, K
MATSUNAGA, J
HIGUCHI, A
ISOBE, M
IIZUKA, T
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1988, 23 (01) : 12 - 19