A RECESSED-GATE INALAS/N+-INP HFET WITH AN INP ETCH-STOP LAYER

We have exploited both the attractive transport properties and the etch selectivity of InP in a novel InAlAs/n+-InP metal-insulator-doped-channel heterostructure FET (MID-FET). In several other material systems, the MIDFET has been shown to be well-suited to high-power telecommunications applications. Our device employs InP both as the channel layer as well as an etch-stop layer in a selective-etch recessed-gate process. L(g) = 1.8-mu-m devices achieve g(m) and I(D,max) values of 224 mS/mm and 408 mA/mm, respectively, the highest reported values for any InP channel HFET with L(g) greater-than-or-equal-to 0.8-mu-m, including MODFET's. These figures combine with a breakdown voltage of 10 V, and peak values of f(T) and f(max) of 10.5 and 28 GHz, respectively. Our selective-etch recessed-gate process contributes to excellent device performance while maintaining a tight 60-mV threshold voltage distribution (13 mV between adjacent devices).