Enhanced channel modulation in dual-gated silicon nanowire transistors

被引:123
作者
Koo, SM [1 ]
Li, QL [1 ]
Edelstein, MD [1 ]
Richter, CA [1 ]
Vogel, EM [1 ]
机构
[1] NIST, Div Semicond Elect, Gaithersburg, MD 20899 USA
关键词
D O I
10.1021/nl051855i
中图分类号
O6 [化学];
学科分类号
0703 ;
摘要
Dual-gated silicon nanowire (SiNW) field-effect transistors (FETs) have been fabricated by using electron-beam lithography. SiNW devices (W approximate to 60 nm) exhibit an on/off current ratio greater than 10(6), which is more than 3 orders of magnitude higher than that of control devices prepared simultaneously having a large channel width (similar to 5 mu m). In addition, by changing the local energy-band profile of the SiNW channel, the top gate is found to suppress ambipolar conduction effectively, which is one of the factors limiting the use of nanotube or nanowire FETs for complimentary logic applications. Two-dimensional numerical simulations show that the gate-induced electrostatic control is improved as the channel width of the FETs decreases. Therefore, enhanced channel modulations can be achieved in these dual-gated SiNW devices.
引用
收藏
页码:2519 / 2523
页数:5
相关论文
共 19 条
[1]   Transition from partial to full depletion in silicon-on-insulator transistors: Impact of channel length [J].
Allibert, F ;
Pretet, J ;
Pananakakis, G ;
Cristoloveanu, S .
APPLIED PHYSICS LETTERS, 2004, 84 (07) :1192-1194
[2]   Band-to-band tunneling in carbon nanotube field-effect transistors [J].
Appenzeller, J ;
Lin, YM ;
Knoch, J ;
Avouris, P .
PHYSICAL REVIEW LETTERS, 2004, 93 (19) :196805-1
[3]   Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering [J].
Bhuwalka, KK ;
Schulze, J ;
Eisele, I .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2005, 52 (05) :909-917
[4]   Functional nanoscale electronic devices assembled using silicon nanowire building blocks [J].
Cui, Y ;
Lieber, CM .
SCIENCE, 2001, 291 (5505) :851-853
[5]   High performance silicon nanowire field effect transistors [J].
Cui, Y ;
Zhong, ZH ;
Wang, DL ;
Wang, WU ;
Lieber, CM .
NANO LETTERS, 2003, 3 (02) :149-152
[6]   Measurement of low Schottky barrier heights applied to metallic source/drain metal-oxide-semiconductor field effect transistors [J].
Dubois, E ;
Larrieu, G .
JOURNAL OF APPLIED PHYSICS, 2004, 96 (01) :729-737
[7]   Electrostatic engineering of nanotube transistors for improved performance [J].
Heinze, S ;
Tersoff, J ;
Avouris, P .
APPLIED PHYSICS LETTERS, 2003, 83 (24) :5038-5040
[8]   A dual-gate-controlled single-electron transistor using self-aligned polysilicon sidewall spacer gates on silicon-on-insulator nanowire [J].
Hu, SF ;
Wu, YC ;
Sung, CL ;
Chang, CY ;
Huang, TY .
IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2004, 3 (01) :93-97
[9]   Silicon nanowires as enhancement-mode Schottky barrier field-effect transistors [J].
Koo, SM ;
Edelstein, MD ;
Li, QL ;
Richter, CA ;
Vogel, EM .
NANOTECHNOLOGY, 2005, 16 (09) :1482-1485
[10]   High inversion current in silicon nanowire field effect transistors [J].
Koo, SM ;
Fujiwara, A ;
Han, JP ;
Vogel, EM ;
Richter, CA ;
Bonevich, JE .
NANO LETTERS, 2004, 4 (11) :2197-2201