Low thermal-budget ultrathin NH3-annealed atomic-layer-deposited Si-nitride/SiO2 stack gate dielectrics with excellent reliability

被引：6

作者：

Khosru, QDM ^{[1
]}

Nakajima, A ^{[1
]}

Yoshimoto, T ^{[1
]}

Yokoyama, S ^{[1
]}

机构：

[1] Hiroshima Univ, Res Ctr Nanodevices & Syst, Higashihiroshima 7398527, Japan

来源：

IEEE ELECTRON DEVICE LETTERS | 2002年 / 23卷 / 04期

关键词：

atomic-layer-deposition; dielectric breakdown; leakage current; NH3-annealing; reliability; trap generation; ultrathin gate dielectrics;

D O I：

10.1109/55.992831

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We present a novel ultrathin (EOT = 2.1 nm) atomic-layer-deposited (ALD) Si-nitride/SiO2 stack gate dielectrics annealed in NH3 at a moderate temperature of 550 degreesC. MOS capacitors are fabricated using the proposed dielectrics. Excellent performances in electrical stressing experiments are shown by the dielectrics. It also exhibited better interface quality, low bulk-trap density, low trap generation rate, and high long-term reliability in comparison with ALD Si-nitride/SiO2 stack dielectrics without NH3 -annealing and conventional thermal SiO2 dielectrics as well. The proposed stack-gate dielectric appears to be very promising for ULS1 devices.

引用

页码：179 / 181

页数：3

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