Evaluation of electrical characteristics and trap-state density in bottom-gate polycrystalline thin film transistors processed with high-pressure water vapor annealing

This paper discusses electrical characteristics and trap-state density in polycrystalline silicon (poly-Si) used in bottom-gate poly-Si thin film transistors (TFTs) processed with high-pressure water vapor annealing (HWA). The threshold voltage uniformity of the HWA-processed TFTs is improved by 42% for N-channel and 38% for P-channel TFTs in terms of standard deviation, and carrier mobility is enhanced by 10% or greater for both N- and P-channel TFTs than those TFTs processed conventionally. Subthreshold swing is also improved by HWA, showing that HWA postannealing is effective for improving the Si/SiO2 interface of the bottom-gate TFTs. Two types of TFTs having different poly-Si crystallinities are examined to investigate barrier transport in poly-Si processed by HWA postannealing. The evaluation of trap-state density for the two types of poly-Si reveals that HWA postannealing is more efficient for N-channel than for P-channel TFTs. Furthermore, HWA postannealing is more effective for poly-Si with high crystallinity to improve TFT characteristics. The analysis of the trapstate distributions and the activation energy of TFT drain current indicate that HWA deactivates dangling bonds highly localized at poly-Si grain boundaries (Gl3s). Thus, HWA postannealing effects can be interpreted by a GB barrier potential model similar to that applied to conventional hydrogenation.