Understanding quasi-ballistic transport in nano-MOSFETs: Part II - Technology scaling along the ITRS

被引：57

作者：

Eminente, S ^{[1
]}

Esseni, D

Palestri, P

Fiegna, C

Selmi, L

Sangiorgi, E

机构：

[1] Univ Udine, DIEGM, I-33100 Udine, Italy

[2] Univ Bologna, DEIS, I-40125 Bologna, Italy

[3] ARCES Ctr, I-40125 Bologna, Italy

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2005年 / 52卷 / 12期

关键词：

back-scattering; ballistic transport; Monte Carlo method (MC); MOSFETs; semiconductor device modeling; silicon-on-insulator (SOI);

D O I：

10.1109/TED.2005.859566

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The on-current and its ballistic limit for MOSFETs designed according to the 2003 International Technology Roadmap for Semiconductors down to the 45-nm node, are evaluated by using the full-band, self-consistent Monte Carlo simulator with quantum-mechanical corrections described in Part I. Our results show that quasi-ballistic transport increases for L-G below approximately 50 nm and contributes most part of the I-ON imrovements related to scaling. Thanks to a lower vertical electric field, double-gate silicon-on-insulator MOSFETs with ultrathin body and low channel doping achieve performance closer to the ballistic limit than the bulk counterparts.

引用

页码：2736 / 2743

页数：8

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