Wafer-level 3D manufacturing issues for streaming video processors

被引：8

作者：

Zeng, AY ^{[1
]}

Lu, JQ ^{[1
]}

Gutmann, RJ ^{[1
]}

Rose, K ^{[1
]}

机构：

[1] Rensselaer Polytech Inst, Ctr Integrated Elect, Troy, NY 12180 USA

来源：

2004 IEEE/SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE AND WORKSHOP: ADVANCING THE SCIENCE AND TECHNOLOGY OF SEMICONDUCTOR MANUFACTURING EXCELLENCE | 2004年

关键词：

high-definition television (HDTV); streaming video; wafer-level 3D integration;

D O I：

10.1109/ASMC.2004.1309576

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

The performance of both 2D and 3D implementations of a streaming video processor is presented incorporating 130nm technology node parameters. The reduced memory access time predicted for the 4MB L2 cache (0.9ns for 3D and 1.65ns for 2D) is indicative of performance advantages projected for 3D implementations of memory-intensive architectures.

引用

页码：247 / 251

页数：5

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