A time digitizer CMOS gate-array with a 250 ps time resolution

A pipelined time digitizer CMOS gate-array has been developed using 0.5 mu m Sea-of-Gate technology. Precise timing signals which are used to sample input signals are generated from 32 taps of an asymmetric ring oscillator, The frequency of the oscillator is controlled by a phase-locked loop (PLL) circuit which runs in the 10-50 MHz frequency range. A test chip has been developed and tested; a time resolution of 250 ps rms at 40 MHz clock was measured. The chip has 4 channels and encoding circuits for both the rising and the falling edges of the input signals. The chip has 128-word dual-port memories, allowing the histories of the input signals to be stored and causing no deadtime for the conversion.