Insertion of a Si layer to reduce operation current for resistive random access memory applications

被引：14

作者：

Chen, Yu-Ting ^{[1
]}

Chang, Ting-Chang ^{[1
,2
,3
]}

Peng, Han-Kuang ^{[4
]}

Tseng, Hsueh-Chih ^{[2
]}

Huang, Jheng-Jie ^{[2
]}

Yang, Jyun-Bao ^{[1
]}

Chu, Ann-Kuo ^{[1
]}

Young, Tai-Fa ^{[4
]}

Sze, Simon M. ^{[2
,5
]}

机构：

[1] Natl Sun Yat Sen Univ, Dept Photon, Kaohsiung 804, Taiwan

[2] Natl Sun Yat Sen Univ, Dept Phys, Kaohsiung 804, Taiwan

[3] Natl Cheng Kung Univ, Adv Optoelect Technol Ctr, Tainan 701, Taiwan

[4] Natl Sun Yat Sen Univ, Dept Mech & Electromech Engn, Kaohsiung 804, Taiwan

[5] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 300, Taiwan

来源：

APPLIED PHYSICS LETTERS | 2013年 / 102卷 / 25期

关键词：

Silicon - Random access storage;

D O I：

10.1063/1.4812304

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

In this study, a reduction of low resistive state (LRS) current is discovered in a V:SiO2/Si bi-layer structure with the addition of a Si layer. A Pt/V:SiO2/TiN structure is fabricated as the standard sample. The results of conduction mechanism analyses for LRS indicate that a SiO2 interfacial layer forms through oxidation of the inserted Si layer after the set process. The LRS current reduction can be attributed to the formation of this SiO2 layer. In addition, self-compliance behavior for the bi-layer structure during the set process further proves the existence of this SiO2 buffer layer in LRS. (C) 2013 AIP Publishing LLC.

引用

页数：3

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