A Si memory device composed of a one-dimensional metal-oxide-semiconductor field-effect-transistor switch and a single-electron-transistor detector

被引:22
作者
Takahashi, Y [1 ]
Fujiwara, A [1 ]
Yamazaki, K [1 ]
Namatsu, H [1 ]
Kurihara, K [1 ]
Murase, K [1 ]
机构
[1] NTT, Basic Res Labs, Atsugi, Kanagawa 2430198, Japan
来源
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS | 1999年 / 38卷 / 4B期
关键词
memory; single electron; Coulomb blockade; subthreshold slope; one-dimensional wire; MOSFET;
D O I
10.1143/JJAP.38.2457
中图分类号
O59 [应用物理学];
学科分类号
摘要
A novel Si memory device composed of a small one-dimensional (1D) Si-wire metal-oxide-semiconductor (MOS) field-effect transistor (FET) and a single-electron transistor (SET) is proposed, and its fundamental characteristics at 40 K are demonstrated. The small Si SET is fabricated by means of pattern-dependent oxidation (PADOX), which is almost completely compatible with Si MOSLSI processes. The 1D MOSFET provides a very steep subthreshold slope that is very close to the physical limit at room temperature in spite of the very short channel. This guarantees low voltage operation as well as small size. The memory device uses a 1D MOSFET as a switch for electrons transported to and from the memory node. The very small number of stored electrons is detected by a highly sensitive SET electrometer. The device can operate with an extremely small number of electrons, which assures ultralow-power and high-speed operation.
引用
收藏
页码:2457 / 2461
页数:5
相关论文
共 12 条
[1]   EVIDENCE OF 2-DIMENSIONAL CARRIER CONFINEMENT IN THIN N-CHANNEL SOI GATE-ALL-AROUND (GAA) DEVICES [J].
COLINGE, JP ;
BAIE, X ;
BAYOT, V .
IEEE ELECTRON DEVICE LETTERS, 1994, 15 (06) :193-195
[2]   Suppression of effects of parasitic metal-oxide-semiconductor field-effect transistors on Si single-electron transistors [J].
Fujiwara, A ;
Takahashi, Y ;
Namatsu, H ;
Kurihara, K ;
Murase, K .
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 1998, 37 (6A) :3257-3263
[3]   A room-temperature silicon single-electron metal-oxide-semiconductor memory with nanoscale floating-gate and ultranarrow channel [J].
Guo, LJ ;
Leobandung, E ;
Chou, SY .
APPLIED PHYSICS LETTERS, 1997, 70 (07) :850-852
[4]   Fast and long retention-time nano-crystal memory [J].
Hanafi, HI ;
Tiwari, S ;
Khan, I .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1996, 43 (09) :1553-1558
[5]   Transistor operation of 30-nm gate-length EJ-MOSFETs [J].
Kawaura, H ;
Sakamoto, T ;
Baba, T ;
Ochiai, Y ;
Fujita, J ;
Matsui, S ;
Sone, J .
IEEE ELECTRON DEVICE LETTERS, 1998, 19 (03) :74-76
[6]   Room temperature operation of Si single-electron memory with self-aligned floating dot gate [J].
Nakajima, A ;
Futatsugi, T ;
Kosemura, K ;
Fukano, T ;
Yokoyama, N .
APPLIED PHYSICS LETTERS, 1997, 70 (13) :1742-1744
[7]   Coulomb blockade effects in edge quantum wire SOI MOSFETs [J].
Ohata, A ;
Toriumi, A ;
Uchida, K .
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 1997, 36 (3B) :1686-1689
[8]   FABRICATION TECHNIQUE FOR SI SINGLE-ELECTRON TRANSISTOR OPERATING AT ROOM-TEMPERATURE [J].
TAKAHASHI, Y ;
NAGASE, M ;
NAMATSU, H ;
KURIHARA, K ;
IWDATE, K ;
NAKAJIMA, K ;
HORIGUCHI, S ;
MURASE, K ;
TABE, M .
ELECTRONICS LETTERS, 1995, 31 (02) :136-137
[9]   Quantized conductance in a small one-dimensional Si wire on a thin silicon-on-insulator substrate fabricated using SiN-film-masked oxidation [J].
Takahashi, Y ;
Fujiwara, A ;
Murase, S .
SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 1998, 13 (09) :1047-1051
[10]   Si memory device operated with a small number of electrons by using a single-electron-transistor detector [J].
Takahashi, Y ;
Fujiwara, A ;
Yamazaki, K ;
Namatsu, H ;
Kurihara, K ;
Murase, K .
ELECTRONICS LETTERS, 1998, 34 (01) :45-46