Electrical properties of Si nanocrystals embedded in an ultrathin oxide

被引:55
作者
Maeda, T [1 ]
Suzuki, E [1 ]
Sakata, I [1 ]
Yamanaka, M [1 ]
Ishii, K [1 ]
机构
[1] Electrotech Lab, Tsukuba, Ibaraki 305, Japan
关键词
D O I
10.1088/0957-4484/10/2/304
中图分类号
TB3 [工程材料学];
学科分类号
0805 ; 080502 ;
摘要
We investigate Si nanocrystals fabricated by the rapid thermal oxidation (RTO) of an ultrathin chemical vapour deposition (CVD) amorphous Si (a-Si:H) film. It is found from the transmission electron microscope (TEM) observation that the ultrathin RTO film contains Si nanocrystals of around or less than 5 nm in size. The dynamic electrical conduction measurement of the RTO diode structure including the Si nanocrystals reveals novel features such as the N-shaped tunnel current versus gate voltage characteristics and the hysteresis. It is also found that the gate voltages at the first and second current rise are fixed and the current reduction in the fixed time interval is observed at the constant gate voltage. These findings can be explained by the fixed-amount electron charging effect at the Si nanocrystals and the consequent screening effect on the tunnel current flowing through the diode structure.
引用
收藏
页码:127 / 131
页数:5
相关论文
共 13 条
  • [1] ELECTRICALLY-ALTERABLE READ-ONLY-MEMORY USING SI-RICH SIO2 INJECTORS AND A FLOATING POLYCRYSTALLINE SILICON STORAGE LAYER
    DIMARIA, DJ
    DEMEYER, KM
    SERRANO, CM
    DONG, DW
    [J]. JOURNAL OF APPLIED PHYSICS, 1981, 52 (07) : 4825 - 4842
  • [2] A room-temperature silicon single-electron metal-oxide-semiconductor memory with nanoscale floating-gate and ultranarrow channel
    Guo, LJ
    Leobandung, E
    Chou, SY
    [J]. APPLIED PHYSICS LETTERS, 1997, 70 (07) : 850 - 852
  • [3] KOHNO A, 1997, P SSDM 97, P567
  • [4] KOHNO A, 1998, 1998 C SOL ST DEV MA, P194
  • [5] OBSERVATION OF QUANTUM EFFECTS AND COULOMB-BLOCKADE IN SILICON QUANTUM-DOT TRANSISTORS AT TEMPERATURES OVER 100 K
    LEOBANDUNG, E
    GUO, LJ
    WANG, Y
    CHOU, SY
    [J]. APPLIED PHYSICS LETTERS, 1995, 67 (07) : 938 - 940
  • [6] Lutzen J., 1997, Silicon Nanoelectronics Workshop 1997. Workshop Abstracts, P24
  • [7] SI-SIO2 INTERFACE - ELECTRICAL PROPERTIES AS DETERMINED BY METAL-INSULATOR-SILICON CONDUCTANCE TECHNIQUE
    NICOLLIA.EH
    GOETZBER.A
    [J]. BELL SYSTEM TECHNICAL JOURNAL, 1967, 46 (06): : 1055 - +
  • [8] NICOLLIAN EH, 1982, MOS PHYSICS TECHNOLO, pCH11
  • [9] FABRICATION TECHNIQUE FOR SI SINGLE-ELECTRON TRANSISTOR OPERATING AT ROOM-TEMPERATURE
    TAKAHASHI, Y
    NAGASE, M
    NAMATSU, H
    KURIHARA, K
    IWDATE, K
    NAKAJIMA, K
    HORIGUCHI, S
    MURASE, K
    TABE, M
    [J]. ELECTRONICS LETTERS, 1995, 31 (02) : 136 - 137
  • [10] Tiwari S, 1996, APPL PHYS LETT, V68, P1377, DOI 10.1063/1.116085