A low-power and low-noise CMOS prescaler for 900 MHz to 1.9 GHz wireless applications

被引：2

作者：

Chang, WH ^{[1
]}

Pehlke, DR ^{[1
]}

Yu, R ^{[1
]}

机构：

[1] Rockwell Int Sci Ctr, Thousand Oaks, CA 91360 USA

来源：

PROCEEDINGS OF THE IEEE 1999 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 1999年

关键词：

D O I：

10.1109/CICC.1999.777352

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A high-speed dual-modulus prescaler has been developed in 0.36-mu m CMOS. The prescaler was designed for low-power frequency synthesizers for 900 MHz to 1.9 GHz wireless applications. It provides programmable division ratio of 64, 65, 128, and 129. Power consumption was 2.9 mW with 1.9 GHz input frequency and 3.3 V power supply. The measured residual phase noises were -142 dBc/Hz at 100 Hz offset and -166 dBc/Hz at 100 kHz offset.

引用

页码：597 / 600

页数：4

共 6 条

[1] A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flops [J].