Interface properties of Si3N4/Si/n-GaAs metal-insulator-semiconductor structure using a Si interlayer

We report the effects of Si interlayer on the capacitance-voltage (C-V) characteristics of Si3N4/Si/n-GaAs metal-insulator-semiconductor (MIS) capacitor as a function of interfacial Si thickness, Si growth temperature and post-growth annealing. The thickness of interfacial Si was found to be the most pivotal parameter for the best interface properties as determined by the comprehensive C-V and conductance measurements. The minimum interface trap density D-it of 5 x 10(10) eV(-1) cm(-2) near midgap is realized with a Si interlayer of 10 Angstrom. The hysteresis and frequency dispersion of the GaAs MIS capacitor were lower than 50 mV, and some of them as low as 30 mV under a field swing of about +/-1.3 MV cm(-1). Ex-situ solid-phase annealing (SPA) at 550 degrees C in N-2 using rapid thermal annealing was sufficient to recrystallize the as-deposited Si interlayer at a low temperature (less than 400 degrees C). The minimum D-it thus obtained using ex-situ SPA was less than 1.5 x 10(11) eV(-1) cm(-2) regardless of Si deposition temperature. 1 MHz frequency response at 80 K requires that the traps be within 35 meV of the conduction band of GaAs. The effects of SPA and post-growth annealing on the interface stability are also discussed.