Negative bias temperature instability in n-channel power VDMOSFETs

被引：26

作者：

Dankovic, D. ^{[1
]}

Manic, I. ^{[1
]}

Davidovic, V. ^{[1
]}

Djoric-Veljkovic, S. ^{[2
]}

Golubovic, S. ^{[1
]}

Stojadinovic, N. ^{[1
]}

机构：

[1] Univ Nis, Fac Elect Engn, Nish 18000, Serbia

[2] Univ Nis, Fac Civil Engn & Architecture, Nish 18000, Serbia

来源：

MICROELECTRONICS RELIABILITY | 2008年 / 48卷 / 8-9期

关键词：

D O I：

10.1016/j.microrel.2008.06.015

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Negative gate bias is used in some applications for faster switching off the n-channel MOS devices. It is shown in this Study that NBT stress-related instability in commercial n-channel power VDMOSFETs could be actually more serious than in corresponding p-channel devices. NBT stress is found to create equal V-T shifts in both device types, whereas the subsequent positive bias annealing results in more serious overall V-T instability in n-channel devices. The changes in the densities of stress-induced interface traps in two device types are equal as well, but significant amounts of NBT stress-induced border traps are only found in n-channel devices. All the results are discussed in terms of hydrogen reaction and diffusion model. (C) 2008 Elsevier Ltd. All rights reserved.

引用

页码：1313 / 1317

页数：5

共 15 条

[1] Exceptional operative gate voltage induces negative bias temperature instability (NBTI) on n-type trench DMOS transistors [J].