The impact of gate oxide scaling (3.2-1.2 nm) on sub-100 nm complementary metal-oxide-semiconductor field-effect transistors

被引:2
作者
Yeh, WK
Lin, CY
机构
[1] Natl Univ Kaohsiung, Dept Elect Engn, Kaohsiung, Taiwan
[2] United Microelect Corp, Technol & Proc Dev Div, Adv Device Dept, Hsinchu, Taiwan
关键词
gate tunneling; nitride oxide; high-dielectric-constant;
D O I
10.1016/S0040-6090(02)00757-5
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
The impact of gate tunneling current on the on-state drive capacities and off-state standby characteristics of complementary metal-oxide-semiconductor field-effect transistors (CMOSFET's) with gate-oxide thicknesses from 3.2 to 1.2 nm was investigated. We examined optimization of nitride gate-oxide thicknesses for device performance of sub-100 nm gate-length CMOSFET's. Device design constraints on gate oxide scaling were also evaluated. Resulting predictions enable verification of nitride oxide limitations prior to replacement of gate insulators using high-permittivity material in sub-100 nm CMOSFET designs. (C) 2002 Elsevier Science B.V. All rights reserved.
引用
收藏
页码:218 / 224
页数:7
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