On the punchthrough phenomenon in submicron MOS transistors

被引:10
作者
Fu, KY [1 ]
Tsang, YL [1 ]
机构
[1] MOTOROLA INC,ADV PROD RES & DEV LAB,AUSTIN,TX 78721
关键词
D O I
10.1109/16.568048
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
s the channel length of MOS transistors reduces to the submicron dimension, the punchthrough becomes more of a surface-initiated and gate-controlled phenomenon, A surface diffusion current (I-sdif) originates from the injection of minority carriers from the source junction due to the combined effect of drain-induced-barrier-lowering (DIBL) and surface-band-bending (Delta phi(so)). The DIBL effect increases rapidly with decreasing channel length, In addition, the extracted Delta phi(so) from the punchthrough current indicates that surface space charges at the source edge shift from the accumulation/depletion mode for long submicron devices (approximate to 0.62 mu m) to the strong-inversion mode for deep submicron devices (approximate to 0.12 mu m). In general, I-sdif dominates over the low drain bias range and eventually converts to the bulk space-charge-limited current (I-scl) as the drain bias increases and the source/drain depletion regions connect, The drain bias for this conversion to occur strongly depends on the channel dimension, Only intermediate submicron devices (approximate to 0.37 mu m) in this study clearly show both the surface and bulk (space-charge-limited) punchthrough components, For long submicron devices, I-sdif essentially dominates, while for deep submicron devices, it converts rapidly to I-scl over the drain bias range investigated, A semi-empirical closed form equation is proposed to describe both I-sdif and I-scl and their merging over the entire range of drain bias, The punchthrough current simulated from this equation shows an excellent agreement with the experimental data.
引用
收藏
页码:847 / 855
页数:9
相关论文
共 21 条
[1]   SHORT-CHANNEL MOSFETS IN THE PUNCHTHROUGH CURRENT MODE [J].
BARNES, JJ ;
SHIMOHIGASHI, K ;
DUTTON, RW .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1979, 26 (04) :446-453
[2]   LOW-LEVEL CURRENTS IN INSULATED GATE FIELD-EFFECT TRANSISTORS [J].
BARRON, MB .
SOLID-STATE ELECTRONICS, 1972, 15 (03) :293-+
[3]   DRAIN VOLTAGE LIMITATIONS OF MOS-TRANSISTORS [J].
BATEMAN, IM ;
ARMSTRONG, GA ;
MAGOWAN, JA .
SOLID-STATE ELECTRONICS, 1974, 17 (06) :539-550
[4]  
CHEN I, 1994, IEEE ELECTR DEVICE L, V15, P9
[5]   THERMIONIC INJECTION AND SPACE-CHARGE-LIMITED CURRENT IN REACH-THROUGH P+NP+ STRUCTURES [J].
CHU, JL ;
SZE, SM ;
PERSKY, G .
JOURNAL OF APPLIED PHYSICS, 1972, 43 (08) :3510-&
[6]   AN ANALYTICAL MODEL OF PUNCHTHROUGH VOLTAGE OF SHORT-CHANNEL MOSFETS WITH NONUNIFORMLY DOPED CHANNELS [J].
DASGUPTA, A ;
LAHIRI, SK .
SOLID-STATE ELECTRONICS, 1990, 33 (04) :395-400
[7]   SURFACE CONDUCTION IN SHORT-CHANNEL MOS DEVICES AS A LIMITATION TO VLSI SCALING [J].
EITAN, B ;
FROHMANBENTCHKOWSKY, D .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1982, 29 (02) :254-266
[8]   Punchthrough currents in sub-micron short channel MOS transistors [J].
Fu, KY ;
Tsang, YL .
SOLID-STATE ELECTRONICS, 1997, 41 (03) :435-439
[9]   NONPLANAR VLSI DEVICE ANALYSIS USING THE SOLUTION OF POISSON EQUATION [J].
GREENFIELD, JA ;
DUTTON, RW .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1980, 27 (08) :1520-1532
[10]  
KLASSEN FM, 1978, SOLID STATE ELECT, V21, P565