DRAIN VOLTAGE LIMITATIONS OF MOS-TRANSISTORS

被引：22

作者：

BATEMAN, IM ^{[1
]}

ARMSTRONG, GA ^{[1
]}

MAGOWAN, JA ^{[1
]}

机构：

[1] QUEENS UNIV BELFAST, DEPT ELECT & ELECT, BELFAST BT7 INN, NORTH IRELAND

来源：

SOLID-STATE ELECTRONICS | 1974年 / 17卷 / 06期

关键词：

D O I：

10.1016/0038-1101(74)90171-3

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：539 / 550

页数：12

共 20 条

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[6]

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LEISTIKO, O ;

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[8] FUNDAMENTAL LIMITATIONS IN MICROELECTRONICS .1. MOS TECHNOLOGY [J].

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[9] SPHERICAL DRILLING - A NEW METHOD FOR MEASUREMENT OF JUNCTION DEPTHS IN SEMICONDUCTOR DEVICES [J].

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[10]

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