A low jitter 0.3-165 MHz CMOS PLL frequency synthesizer for 3 V/5 V operation

This paper describes a phase-locked loop (PLL)-based frequency synthesizer, The voltage-controlled oscillator (VCO) utilizing a ring of single-ended current-steering amplifiers (CSA) provides low noise, wide operating frequencies, and operation over a wide range of power supply voltage, A programmable charge pump circuit automatically configures the loop gain and optimizes it over the whole frequency range, The measured PLL frequency ranges are 0.3-165 MHz and 0.3-100 MHz at 5 V and 3 V supplies, respectively (the VCO frequency is twice PLL output), The peak-to-peak jitter is 81 ps (13 ps rms) at 100 MHz, The chip is fabricated with a standard 0.8-mu m n-well CMOS process.