All perovskite Capacitor (APEC) technology for (Ba,Sr)TiO3 capacitor scaling toward 0.10μm stacked DRAMs

被引：35

作者：

Hieda, K ^{[1
]}

Eguchi, K ^{[1
]}

Fukushima, N ^{[1
]}

Aoyama, T ^{[1
]}

Natori, K ^{[1
]}

Kiyotoshi, M ^{[1
]}

Yamazaki, S ^{[1
]}

Izuha, M ^{[1
]}

Niwa, S ^{[1
]}

Fukuzumi, Y ^{[1
]}

Ishibashi, Y ^{[1
]}

Kohyama, Y ^{[1
]}

Arikado, T ^{[1
]}

Okumura, K ^{[1
]}

机构：

[1] Toshiba Corp, Microelect Eng Lab, Isogo Ku, Yokohama, Kanagawa 2358522, Japan

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST | 1998年

关键词：

D O I：

10.1109/IEDM.1998.746478

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

All perovskite Capacitor (APEC) technology is proposed to achieve (Ba, Sr)TiO3(BST) capacitor scaling toward 0.10 mu m DRAM generation. A conductive perovskite-oxide (polycrystalline SrRuO3 (SRO)) electrode is introduced as a bottom and a top electrode of BST capacitor. Advantages of APEC technology are low leakage current and less damage to hydrogen-annealing. A new BST-CVD tool with a good film uniformity is also developed to realize a BST film thickness decrease. Both APEC and the new BST-CVD tool are found to be a promising technology for future BST capacitors scaling.

引用

页码：807 / 810

页数：4

共 5 条

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