Very low Schottky barrier to n-type silicon with PtEr-stack silicide

被引:38
作者
Tang, XH
Katcki, J
Dubois, E
Reckinger, N
Ratajczak, J
Larrieu, G
Loumaye, P
Nisole, O
Bayot, V
机构
[1] Catholic Univ Louvain, Microelect Lab, B-1348 Louvain, Belgium
[2] Catholic Univ Louvain, Res Ctr Micro & Nanoscop Mat & Elect Devices, B-1348 Louvain, Belgium
[3] Inst Electr Mat Technol, PL-02668 Warsaw, Poland
[4] IEMN, ISEN, UMR CNRS 8520, F-59652 Villeneuve Dascq, France
关键词
Schottky barrier MOSFET; PtEr-stack silicide system; rapid thermal annealing; Schottky barrier height; silicon series resistance;
D O I
10.1016/S0038-1101(03)00256-9
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We investigate Er silicide formed on n-type silicon. In order to protect the Er from oxidation during the formation of Er silicide in non-UHV conditions, a Pt layer is deposed successively on top of Er layer. Surprisingly, we observe that Pt remains essentially unaffected in the formation of Er silicide at temperatures lower than 700 degreesC. We find that silicidation process is fully completed by rapid thermal annealing at 500 degreesC. A simplified method of analysis considering the final Schottky barrier MOSFET application has been used to characterize the Schottky barrier of the PtEr-stack silicide system. A very low apparent Schottky barrier (smaller than 0.1 eV) on a n-type silicon substrate with a concentration of 1.4 x 10(16) cm(-3) in the active region has been obtained. (C) 2003 Elsevier Ltd. All rights reserved.
引用
收藏
页码:2105 / 2111
页数:7
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