Low Schottky barrier source/drain for advanced MOS architecture: device design and material considerations

被引：41

作者：

Dubois, E ^{[1
]}

Larrieu, G ^{[1
]}

机构：

[1] IEMN, ISEN, CNRS, UMRS 8520, F-59652 Villeneuve Dascq, France

来源：

SOLID-STATE ELECTRONICS | 2002年 / 46卷 / 07期

关键词：

D O I：

10.1016/S0038-1101(02)00033-3

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An alternative MOSFET architecture based on the use of low barrier Schottky source/drain (S/D) contacts coupled to a thin silicon-on-insulator (Sol) film is described. Two-dimensional device simulations are used to demonstrate the advantage of low Schottky barrier S/D over conventional implanted technologies in terms of current drive capabilities. It is shown that the silicide penetration in the silicon does not increase the contact resistance for this structure while a severe degradation of the current drive is observed for conventional MOS architectures. Experiments conducted on Pt/ Ge metallic stacks on p-type silicon show that very low Schottky barriers to hole can be obtained (similar to50 meV). (C) 2002 Elsevier Science Ltd. All rights reserved.

引用

页码：997 / 1004

页数：8

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