Investigation of anomalous inversion C-V characteristics for long-channel MOSFETs with leaky dielectrics:: Mechanisms and reconstruction

被引:2
作者
Lee, Wei [1 ]
Su, Pin [1 ]
Su, Ke-Wei [2 ]
Chiang, Chung-Shi [2 ]
Liu, Sally [2 ]
机构
[1] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 300, Taiwan
[2] Taiwan Seminconductor Mfg Co, Hsinchu 300, Taiwan
关键词
capacitance-voltage (C-V); intrinsic input resistance; metal-oxide-emiconductor (MOS) capacitance; MOSFET; ultrathin gate oxide; CAPACITANCE EXTRACTION; THICKNESS EXTRACTION; OXIDE THICKNESS;
D O I
10.1109/TSM.2007.914374
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
This paper investigates anomalous inversion capacitance-voltage (C-V) attenuation for MOSFETs with leaky dielectrics. We propose to reconstruct the inversion C-V characteristic based on long-channel MOSFETs using the concept of intrinsic input resistance (R-ii). The concept of R-ii has been validated by segmented BSIM4/SPICE simulation. Our reconstructed C-V characteristics show poly-depletion effects, which are not visible in the two-frequency three-element method and agree well with the North Carolina State University-CVC simulation results. The intrinsic input resistance dominates the overall gate-current-induced debiasing effect (similar to 95% for L = 20 mu m) and can be extracted directly from the I-V characteristics. Due to its simplicity, our proposed R-ii approach may provide an option for regular process monitoring purposes.
引用
收藏
页码:104 / 109
页数:6
相关论文
共 23 条
[1]  
*AG TECHN, PN422943 AG TECHN
[2]   Impact of tunnel currents and channel resistance on the characterization of channel inversion layer charge and polysilicon-gate depletion of sub-20-Å gate oxide MOSFET's [J].
Ahmed, K ;
Ibok, E ;
Yeap, GCF ;
Xiang, Q ;
Ogle, B ;
Wortman, JJ ;
Hauser, JR .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1999, 46 (08) :1650-1655
[3]   Inversion MOS capacitance extraction for high-leakage dielectrics using a transmission line equivalent circuit [J].
Barlage, DW ;
O'Keeffe, JT ;
Kavalieros, JT ;
Nguyen, MM ;
Chau, RS .
IEEE ELECTRON DEVICE LETTERS, 2000, 21 (09) :454-456
[4]   Capacitance reconstruction from measured C-V in high leakage, nitride/oxide MOS [J].
Choi, CH ;
Wu, Y ;
Goo, JS ;
Yu, ZP ;
Dutton, RW .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2000, 47 (10) :1843-1850
[5]   Improved method for the oxide thickness extraction in MOS structures with ultrathin gate dielectrics [J].
Ghibaudo, G ;
Bruyère, S ;
Devoivre, T ;
DeSalvo, B ;
Vincent, E .
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 2000, 13 (02) :152-158
[6]   Extending two-element capacitance extraction method toward ultraleaky gate oxides using a short-channel length [J].
Goo, JS ;
Mantei, T ;
Wieczorek, K ;
En, WG ;
Icel, AB .
IEEE ELECTRON DEVICE LETTERS, 2004, 25 (12) :819-821
[8]   Estimating oxide thickness of tunnel oxides down to 1.4 nm using conventional capacitance-voltage measurements on MOS capacitors [J].
Henson, WK ;
Ahmed, KZ ;
Vogel, EM ;
Hauser, JR ;
Wortman, JJ ;
Venables, RD ;
Xu, M ;
Venables, D .
IEEE ELECTRON DEVICE LETTERS, 1999, 20 (04) :179-181
[9]   An effective gate resistance model for CMOS RF and noise modeling [J].
Jin, XD ;
Ou, JJ ;
Chen, CH ;
Liu, WD ;
Deen, MJ ;
Gray, PR ;
Hu, CM .
INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST, 1998, :961-964
[10]   Elimination of chuck-related parasitics in MOSFET gate capacitance measurements [J].
Kraus, PA ;
Ahmed, KZ ;
Williamson, JS .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2004, 51 (08) :1350-1352