A capacitor-less DRAM cell on 75nm gate length, 16nm thin fully depleted SOI device for high density embedded memories

被引：52

作者：

Ranica, R ^{[1
]}

Villaret, A ^{[1
]}

Fenouillet-Beranger, C ^{[1
]}

Malinge, P ^{[1
]}

Mazoyer, P ^{[1
]}

Masson, P ^{[1
]}

Delille, D ^{[1
]}

Charbuillet, C ^{[1
]}

Candelier, P ^{[1
]}

Skotnicki, T ^{[1
]}

机构：

[1] STMicroelect, F-38926 Crolles, France

来源：

IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST | 2004年

关键词：

D O I：

10.1109/IEDM.2004.1419131

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A capacitor-less DRAM cell on very thin film (Tsi = 16nm) and short gate length (Lg = 75nm) Fully Depleted (FD) device is demonstrated for the first time. Memory operations mechanisms are presented and retention time compatible to eDRAM requirements is measured at 85degreesC Non destructive reading is demonstrated at 25degreesC and disturb margins are deeply investigated, showing the possibility of matrix integration. This study is then extended to another type of FD device: the very promising Double Gate architecture.

引用

页码：277 / 280

页数：4

共 14 条

[1] REDUCTION OF KINK EFFECT IN THIN-FILM SOI MOSFETS [J].