A study of cycling induced degradation mechanisms in Si nanocrystal memory devices

被引：30

作者：

Jiang, Dandan ^{[1
,2
]}

Zhang, Manhong ^{[1
]}

Huo, Zongliang ^{[1
]}

Wang, Qin ^{[1
]}

Liu, Jing ^{[1
]}

Yu, Zhaoan ^{[1
]}

Yang, Xiaonan ^{[1
]}

Wang, Yong ^{[1
]}

Zhang, Bo ^{[3
]}

Chen, Junning ^{[2
]}

Liu, Ming ^{[1
]}

机构：

[1] Chinese Acad Sci, Inst Microelect, Beijing 100029, Peoples R China

[2] Anhui Univ, Sch Elect Sci & Technol, Hefei 230039, Peoples R China

[3] Grace Semicond Mfg Corp, Shanghai 201203, Peoples R China

来源：

NANOTECHNOLOGY | 2011年 / 22卷 / 25期

基金：

中国国家自然科学基金;

关键词：

OXIDE CHARGE; INTERFACE TRAPS;

D O I：

10.1088/0957-4484/22/25/254009

中图分类号：

TB3 [工程材料学];

学科分类号：

0805 ; 080502 ;

摘要：

The endurance of Si nanocrystal memory devices under Fowler-Nordheim program and erase (P/E) cycling is investigated. Both threshold voltage (V-th) and subthreshold swing (SS) degradation are observed when using a high program or erase voltage. The change of SS is found to be proportional to the shift of V-th, indicating that the generation of interface traps plays a dominant role. The charge pumping and the mid-gap voltage methods have been used to analyze endurance degradation both qualitatively and quantitatively. It is concluded that high erase voltage causes severe threshold voltage degradation by generating more interface traps and trapped oxide charges.

引用

页数：5

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