Concurrent thermal and electrical modeling of sub-micrometer silicon devices

High electric fields, that are characteristic of sub-micron devices, produce highly energetic electrons, lack of equilibrium between electrons, optical phonons, and acoustic phonons, and high rates of heat generation. A simple coupled thermal and electrical model is developed for sub-micron silicon semiconductor devices consisting of the hydrodynamic equations for electron transport and energy conservation equations for different phonon modes. An electron Reynolds number is proposed and used to simplify the electron momentum equation. On a case study of the metal-oxide-semiconductor field-effect transistor with 0.24 mu m gate length, the calculated transconductance of 0.175 1/Omega m agreed well with measured value of 0.180 1/Omega m at 2 V drain voltage. The maximum electron temperature is found to occur under the drain side of the gate where the electric field is the highest. Comparison with experimental data shows the predictions of optical and acoustic phonon temperature distributions to have the correct trend and the observed asymmetric behavior. Increase iri substrate boundary temperature by 100 degrees C reduces the drain current by 17% and decreases the maximum electron temperature by 8%. The first effect increases device delay and the second effect decreases the possibility of device degradation by charge trapping in the gate oxide. (C) 1996 American Institute of Physics.