Demystifying 3D ICs: The procs and cons of going vertical

被引：498

作者：

Davis, WR ^{[1
]}

Wilson, J ^{[1
]}

Mick, S ^{[1
]}

Xu, M ^{[1
]}

Hua, H ^{[1
]}

Mineo, C ^{[1
]}

Sule, AM ^{[1
]}

Steer, M ^{[1
]}

Franzon, PD ^{[1
]}

机构：

[1] N Carolina State Univ, Dept Elect & Comp Engn, Raleigh, NC 27695 USA

来源：

IEEE DESIGN & TEST OF COMPUTERS | 2005年 / 22卷 / 06期

关键词：

D O I：

10.1109/MDT.2005.136

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

As 3D technologies become technologically viable, there is increasing interest in determining the achievable payoff. This article first presents an overview of 3D technologies and introduces the motivation for moving from 2D to 3D. It then presents a case study of a fast-Fourier-transform design to illustrate the advantages of going to the third dimension. © 2005 IEEE.

引用

页码：498 / 510

页数：13

共 14 条

[1] [Anonymous], METIS SERIAL GRAPH P
[2] 3D processing technology and its impact on iA32 microprocessors
Black, B
Nelson, DW
Webb, C
Samra, N
[J]. IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS & PROCESSORS, PROCEEDINGS, 2004, : 316 - 318
[3] Das S, 2003, ASP-DAC 2003: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, P53, DOI 10.1109/ASPDAC.2003.1194993
[4] Proximity communication
Drost, RJ
Hopkins, RD
Ho, R
Sutherland, IE
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (09) : 1529 - 1535
[5] Through wafer interconnects on active pmos devices
Johnson, VN
Jozwiak, J
Moll, A
[J]. 2004 IEEE WORKSHOP ON MICROELECTRONIC AND ELECTRON DEVICES, 2004, : 82 - 84
[6] Kanda K, 2003, ISSCC DIG TECH PAP I, V46, P186
[7] KIM T, 2004, P S MAT INT PACK ISS, V833
[8] A 3-D stacked chip packaging solution for miniaturized massively parallel processing
Lea, RM
Jalowiecki, IP
Boughton, DK
Yamaguchi, JS
Pepe, AA
Ozguz, VH
Carson, JC
[J]. IEEE TRANSACTIONS ON ADVANCED PACKAGING, 1999, 22 (03): : 424 - 432
[9] 4 Gbps high-density AC coupled interconnection (Invited paper)
Mick, S
Wilson, J
Franzon, P
[J]. PROCEEDINGS OF THE IEEE 2002 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2002, : 133 - 140
[10] MIRUA N, 2004, P IEEE CUST INT CIRC, P99

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