2 Mb SPRAM (SPin-transfer torque RAM) with bit-by-bit bi-directional current write and parallelizing-direction current read

被引：174

作者：

Kawahara, Takayuki ^{[1
]}

Takemura, Riichiro ^{[1
]}

Miura, Katsuya ^{[2
]}

Hayakawa, Jun ^{[2
]}

Ikeda, Shoji ^{[3
,4
]}

Lee, Young Min ^{[3
,4
]}

Sasaki, Ryutaro ^{[3
,4
]}

Goto, Yasushi ^{[1
]}

Ito, Kenchi ^{[2
]}

Meguro, Toshiyasu ^{[3
,4
]}

Matsukura, Fumihiro ^{[3
,4
]}

Takahashi, Hiromasa ^{[2
]}

Matsuoka, Hideyuki ^{[2
]}

Ohno, Hideo ^{[3
,4
]}

机构：

[1] Hitachi Ltd, Ctr Res Lab, Tokyo 1858601, Japan

[2] Hitachi Ltd, Adv Res Lab, Tokyo 1858601, Japan

[3] Tohoku Univ, Lab Nanoelect, Tokyo, Miyagi 9808577, Japan

[4] Tohoku Univ, Sprintron Res Inst Elect Commun, Tokyo, Miyagi 9808577, Japan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2008年 / 43卷 / 01期

关键词：

bi-directional current write parallelizing direction current read; low-power RAM; nonvolatile RAM; spin-transfer torque; TMR; universal memory;

D O I：

10.1109/JSSC.2007.909751

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 1.8 V 2 Mb SPin-transfer torque RAM (SPRAM) chip using a 0.2 mu m logic process with an MgO tunneling barrier cell demonstrates the circuit technologies for potential low-power nonvolatile RAM, or universal memory. This chip features an array scheme with bit-by-bit bi-directional current writing to achieve proper spin-transfer torque writing of 100 ns, and parallelizing-direction current reading with a low-voltage bit-line for preventing read disturbances that lead to 40 ns access time.

引用

页码：109 / 120

页数：12

共 13 条

[1] A 4-Mb 0.18-μm 1T1MTJ toggle MRAM with balanced three input sensing scheme and locally mirrored unidirectional write drivers [J].