Power-aware microarchitecture:: Design and modeling challenges for next-generation microprocessors

被引：258

作者：

Brooks, DM ^{[1
]}

Bose, P ^{[1
]}

Schuster, SE ^{[1
]}

Jacobson, H ^{[1
]}

Kudva, PN ^{[1
]}

Buyuktosunoglu, A ^{[1
]}

Wellman, JD ^{[1
]}

Zyuban, V ^{[1
]}

Gupta, M ^{[1
]}

Cook, PW ^{[1
]}

机构：

[1] IBM Corp, Thomas J Watson Res Ctr, Yorktown Hts, NY 10598 USA

来源：

IEEE MICRO | 2000年 / 20卷 / 06期

关键词：

CMOS integrated circuits - Computer simulation - Computer workstations - Design - Electric power supplies to apparatus - Mathematical models - Microprocessor chips - Performance;

D O I：

10.1109/40.888701

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

THE ABILITY TO ESTIMATE POWER CONSUMPTION DURING EARLY-STAGE DEFINITION AND TRADE-OFF STUDIES IS A KEY NEW METHODOLOGY ENHANCEMENT. OPPORTUNITIES FOR SAVING POWER CAN BE EXPOSED VIA MICROARCHITECTURE-LEVEL MODELING, PARTICULARLY THROUGH CLOCK-GATING AND DYNAMIC ADAPTATION.

引用

页码：26 / 44

页数：19

共 22 条

[1] Design challenges of technology scaling [J].

Borkar, S .

IEEE MICRO, 1999, 19 (04) :23-29

[2]

Brooks D, 2000, PROCEEDING OF THE 27TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, P83, DOI [10.1145/342001.339657, 10.1109/ISCA.2000.854380]

[3]

Burger D., 1997, Computer Architecture News, V25, P13, DOI 10.1145/268806.268810

[4]

DIEFENDORFF K, 1999, MICROPROCESSOR 1006, P11

[5] Deep-submicron microprocessor design issues [J].

Flynn, MJ ;

Hung, P ;

Rudd, KW .

IEEE MICRO, 1999, 19 (04) :11-22

[6] Energy dissipation in general purpose microprocessors [J].

Gonzalez, R ;

Horowitz, M .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996, 31 (09) :1277-1284

[7]

Gowan MK, 1998, 1998 DESIGN AUTOMATION CONFERENCE, PROCEEDINGS, P726, DOI 10.1109/DAC.1998.724567

[8] Energy optimization of multilevel cache architectures for RISC and CISC processors [J].

Ko, U ;

Balsara, T ;

Nanda, AK .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 1998, 6 (02) :299-308

[9] Environment for PowerPC microarchitecture exploration [J].

Moudgill, M ;

Wellman, JD ;

Moreno, JH .

IEEE MICRO, 1999, 19 (03) :15-25

[10] Validation of Turandot, a fast processor model for microarchitecture exploration [J].

Moudgill, M ;

Bose, P ;

Moreno, JH .

1999 IEEE INTERNATIONAL PERFORMANCE, COMPUTING AND COMMUNICATIONS CONFERENCE, 1999, :451-457

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