Bias temperature instability in scaled p+ polysilicon gate p-MOSFET's

The bias temperature instability in surface-channel p(+) polysilicon gate p-MOSFET's was evaluated. It was found that a large negative threshold voltage shift (Delta V-th,BT) is induced by negative bias temperature (BT) stress in short-channel p(+) polysilicon gate p-MOSFET's, This Vth shift, which depends on the gate length of p-MOSFET's, is a new degradation mode. In this degradation, the negative Delta V-th, BT increases significantly with a reduction in the gate length, It was shown that this is because of the local degradation of the gate oxide near the gate edge, This degradation is caused by the electrochemical reaction between holes and oxide defects and it is enhanced by boron penetration through the gate oxide from p(+)-gate. For the bias temperature instability in p(+)-gate p-MOSFET's, sufficient care should be taken in scaled dual-gate CMOS devices.