Substrate Gating of Contact Resistance in Graphene Transistors

被引：45

作者：

Berdebes, Dionisis ^{[1
]}

Low, Tony ^{[2
]}

Sui, Yang ^{[3
]}

Appenzeller, Joerg ^{[1
]}

Lundstrom, Mark S. ^{[1
]}

机构：

[1] Purdue Univ, Network Computat Nanotechnol, Birck Nanotechnol Ctr, Sch Elect & Comp Engn, W Lafayette, IN 47906 USA

[2] IBM Corp, TJ Watson Res Ctr, Yorktown Hts, NY 10598 USA

[3] GE Global Res Ctr, Niskayuna, NY 12309 USA

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2011年 / 58卷 / 11期

关键词：

Contacts; graphene transistor; Landauer; nonequilibrium Green's function (NEGF); quantum transport; LIMITS; GAS;

D O I：

10.1109/TED.2011.2163800

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Metal contacts have been identified to be a key technological bottleneck for the realization of viable graphene electronics. Recently, it has been observed that for structures that possess both a top and a bottom gate, the electron-hole conductance asymmetry can be modulated by the bottom gate. In this paper, we explain this observation by postulating the presence of an effective thin interfacial dielectric layer between the metal contact and the underlying graphene. Electrical results from quantum transport calculations accounting for this modified electrostatics corroborate well with the experimentally measured contact resistances. This paper indicates that the engineering of a metal-graphene interface is a crucial step toward reducing the contact resistance for high-performance graphene transistors.

引用

页码：3925 / 3932

页数：8

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