Robust bi-stable memory operation in single-layer graphene ferroelectric memory

被引:145
作者
Song, Emil B. [1 ]
Lian, Bob [1 ]
Kim, Sung Min [1 ]
Lee, Sejoon [1 ,2 ]
Chung, Tien-Kan [3 ]
Wang, Minsheng [1 ]
Zeng, Caifu [1 ]
Xu, Guangyu [1 ]
Wong, Kin [1 ]
Zhou, Yi [1 ]
Rasool, Haider I. [4 ]
Seo, David H. [5 ]
Chung, Hyun-Jong [5 ]
Heo, Jinseong [5 ]
Seo, Sunae [6 ]
Wang, Kang L. [1 ]
机构
[1] Univ Calif Los Angeles, Dept Elect Engn, Los Angeles, CA 90095 USA
[2] Dongguk Univ Seoul, Quantum Funct Semicond Res Ctr, Seoul 100715, South Korea
[3] Natl Chiao Tung Univ, Dept Mech Engn, Hsinchu 300, Taiwan
[4] Univ Calif Los Angeles, Dept Chem & Biochem, Los Angeles, CA 90095 USA
[5] Samsung Adv Inst Technol, Yongin 446712, Gyeonggi, South Korea
[6] Sejong Univ, Dept Phys, Seoul 143747, South Korea
关键词
D O I
10.1063/1.3619816
中图分类号
O59 [应用物理学];
学科分类号
摘要
With the motivation of realizing an all graphene-based circuit for low power, we present a reliable nonvolatile graphene memory device, single-layer graphene (SLG) ferroelectric field-effect transistor (FFET). We demonstrate that exfoliated single-layer graphene can be optically visible on a ferroelectric lead-zirconate-titanate (PZT) substrate and observe a large memory window that is nearly equivalent to the hysteresis of the PZT at low operating voltages in a graphene FFET. In comparison to exfoliated graphene, FFETs fabricated with chemical vapor deposited (CVD) graphene exhibit enhanced stability through a bi-stable current state operation with long retention time. In addition, we suggest that the trapping/de-trapping of charge carriers in the interface states is responsible for the anti-hysteresis behavior in graphene FFET on PZT. (C) 2011 American Institute of Physics. [doi:10.1063/1.3619816]
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页数:3
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