A 180 Kbit embeddable MRAM memory module

A 180 Kbit magnetoresistive random access memory (MRAM) organized as 22 bits by 8 Kwords has been developed for embedding in a 0.28 micron CMOS process. The memory cell is based on a 1-transistor 1-magnetic tunnel junction (1T1MTJ) bit cell with a toggle MTJ. For reads, the memory is architected with word lines connecting a row of bits to bit lines with a pass transistor and two stages of columns selection transistors connecting bit lines to dual sense amplifiers. For writes, a read is first performed to determine the state of bits to be written followed by a toggle decision to enable bit line toggle drivers. Overlapping bit and word line currents toggle the selected bits. The new dual sense amplifier architecture separates the amplifier reference bits from the bias bits thereby improving sensitivity and reducing offset. The write driver uses a switched capacitor and charge sharing to improve ground bounce immunity and reduce area. Embedded test registers control internal memory timing, reference voltages, reference currents and access features enabling detailed characterization of the memory and optimization of the design. An example describing optimization of the write parameters is presented.