Design considerations of high-κ gate dielectrics for sub-0.1-μm MOSFET's

被引：27

作者：

Cheng, BH ^{[1
]}

Cao, M

Vande Voorde, P

Greene, W

Stork, H

Yu, ZP

Woo, JCS

机构：

[1] Univ Calif Los Angeles, Dept Elect Engn, Los Angeles, CA 90095 USA

[2] Hewlett Packard Labs, ULSI Res Lab, Palo Alto, CA 94304 USA

[3] Stanford Univ, Ctr Integrated Syst, Stanford, CA 94305 USA

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 1999年 / 46卷 / 01期

关键词：

D O I：

10.1109/16.737469

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The potential impact of high-kappa gate dielectrics on device short-channel performance is studied over a wide range of dielectric permittivities. It is shown that the short-channel performance degradation caused by the fringing fields from the gate to the source/drain regions, is mainly determined by the gate thickness-to-length aspect ratio. In addition, the gate stack configuration also plays an important role in the determination of the device short-channel performance degradation.

引用

页码：261 / 262

页数：2

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