Ultra-thin gate oxides - Performance and reliability

被引：42

作者：

Iwai, H ^{[1
]}

Momose, HS ^{[1
]}

机构：

[1] Toshiba Corp, Microelect Engn Lab, Saiwai Ku, Kawasaki, Kanagawa 2108582, Japan

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST | 1998年

关键词：

D O I：

10.1109/IEDM.1998.746307

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Gate oxide thinning accompanied by the CMOS downsizing is expected to reach a direct-tunneling leakage current regime at the generations of 0.1 mu m and below. This has been regarded as one of the limiting factor of CMOS progress in terms of performance. Recently, the studies of the direct-tunneling gate oxide have been carried out popularly and aggressively. In this paper, the results of these studies are reviewed and future prospects for the gate oxides are predicted.

引用

页码：163 / 166

页数：4

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